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features ? programmable 4,194,304 x 1 and 8,388,608 x 1-bit serial memories designed to store configuration programs for field programmable gate arrays (fpgas) 3.3v output capability 5v tolerant i/o pins program support using the atmel atdh220 0e system or industry third party programmers in-system programmable (isp) via 2-wire bus simple interface to sram fpgas compatible with atmel at40k and at94k devices, altera ? flex ? , excalibur ? , stratix ? , cyclone ? and apex ? devices cascadable read-back to support additional configurations or higher-density arrays low-power cmos flash process available in 8-lead lap, 20-lead plcc and 32-lead tqfp packages emulation of atmel?s at24cxxx serial eeproms low-power standby mode single device capable of holding 4 bit stream files allowing simple system reconfiguration fast serial download speeds up to 33 mhz endurance: 5,000 write cycles typical green (lead/halide-free/rohs compliant) packages 1. description the at17fxxxa series of in-system pr ogrammable configuration proms (configu- rators) provide an easy-to-use, cost-effe ctive configuration memory for field programmable gate arrays. the at17fxxxa series device is packaged in the 8-lead lap, 20-lead plcc and 32-lead tqfp, see table 1-1 . the at17fxxxa series con- figurator uses a simple serial-access pr ocedure to configure one or more fpga devices. the at17fxxxa series configurators can be programmed with industry-standard pro- grammers, atmel?s atdh2200e programmi ng kit or atmel?s atdh2225 isp cable. table 1-1. at17fxxxa series packages package at17f040a at17f080a 8-lead lap yes yes 20-lead plcc yes yes 32-lead tqfp yes yes fpga configuration flash memory at17f040a at17f080a 2823d?cnfg?2/08
2 2823d?cnfg?2/08 at17f040a/080a 2. pin configuration 8-lead lap 20-lead plcc 32-lead tqfp 8 7 6 5 1 2 3 4 data dclk reset/oe ncs vcc ser_en (a2) ncasc gnd 4 5 6 7 8 18 17 16 15 14 dclk nc nc pagesel1 reset/oe ser_en nc page_en ready nc 3 2 1 20 19 9 10 11 12 13 ncs gnd pagesel0 (a2) ncasc nc nc data nc vcc nc 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc dclk nc nc nc pagesel1 reset/oe nc nc ser_en nc page_en ready nc nc nc 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 nc ncs nc gnd nc pagesel0 (a2) ncasc nc nc data nc nc nc vcc nc nc
3 2823d?cnfg?2/08 at17f040a/080a 3. block diagram 4. device description the control signals for the confi guration memory device (ncs, reset /oe and dclk) interface directly with the fpga device c ontrol signals. all fpga devices can control the entire configura- tion process and retrieve data from the confi guration device without requiring an external intelligent controller. the reset /oe and ncs pins control the tri-state buffer on the data output pin and enable the address counter. when reset /oe is driven low, the configuration device resets its address counter and tri-states its data pin. the ncs pin also controls the output of the at17fxxxa series configurator. if ncs is held high after the reset /oe reset pulse, the counter is disabled and the data output pin is tri-stated. when oe is subsequently driven hi gh, the counter and the data output pin are enabled. when reset /oe is driven low again, the address counter is reset and the data output pin is tri-st ated, regardless of the state of ncs. when the configurator has driven out all of it s data and ncasc is driven low, the device tri- states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. config. page select power-on reset flash memory clock/oscillator logic 2-wire serial programming serial download logic control logic dclk ncasc(a2) data ncs reset/oe ser_e n ce/we/oe data address ready page_e n pagesel0 pagesel1 reset
4 2823d?cnfg?2/08 at17f040a/080a 5. pin description 5.1 data (1) three-state data output for fpga configuration. open-collector bi-directional pin for configura- tion programming. 5.2 dclk (1) three-state clock. functions as an input when the configurator is in programming mode (i.e. ser_en is low) and as an output during fpga configuration. 5.3 page_en (2) input used to enable page download mode. when page_en is high the configuration download address space is partitioned into 4 equal pages. this gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. this input works in conjunction with the pagesel inputs. page_en must be remain low if paging is not desired. when ser_en is low (isp mode) this pin has no effect. notes: 1. this pin has an internal 20 k ? pull-up resistor. 2. this pin has an internal 30 k ? pull-down resistor. table 5-1. pin description name i/o at17f040a/080a 20 plcc 32 tqfp data i/o 2 31 dclk i 4 2 page_en i 16 21 pagesel0 i 11 14 pagesel1 i 7 6 reset / oe i8 7 ncs i 9 10 gnd ? 10 12 ncasc o 12 15 a2 i ready o 15 20 ser_en i18 23 v cc ?20 27
5 2823d?cnfg?2/08 at17f040a/080a 5.4 pagesel[1:0] (2) page select inputs. used to determine which of the 4 memory pages are targeted during a serial configuration download. the address spac e for each of the pages is shown in table 5-2 . when ser_en is low (isp mode) thes e pins have no effect. 5.5 reset /oe (1) output enable (active high) and reset (active low) when ser_en is high. a low level on reset /oe resets both the address and bit counters . a high level (with ncs low) enables the data output driver. 5.6 ncs (1) chip enable input (active low). a low level (with oe high) allows dclk to increment the address counter and enables the data output driv er. a high level on ncs disables both the address and bit counters and forces the device into a low-power standby mode. note that this pin will not enable/disable the device in the 2-wire serial programming mode (ser_en low). 5.7 gnd ground pin. a 0.2 f dec oupling capacitor between v cc and gnd is recommended. 5.8 ncasc cascade select output (when ser_en is high). this output goes low when the internal address counter has reached its maximum value. if the page_en input is set high, the maxi- mum value is the highest address in the select ed partition. the pagesel [1:0] inputs are used to make the 4 partition selections. if the page_en input is set low, the device is not partitioned and the address maximum value is th e highest address in the device, see table 5-2 on page 5 . in a daisy chain of at17fxxxa series devices, th e ncasc pin of one device must be connected to the ncs input of the next device in the chain. it will stay low as long as ncs is low and oe is high. it will then follow ncs until oe goes low; thereafter, ncasc will stay high until the entire eeprom is read again. 5.9 a2 (1) device selection input, (when ser_en low). the input is used to enable (or chip select) the device during programming (i.e., when ser_en is low). refer to the at17fxxxa programming specification available on the atme l web site for additional details. notes: 1. this pin has an internal 20 k pull-up resistor. 2. this pin has an internal 30 k ? pull-down resistor. table 5-2. address space paging decodes at17f040a (4 mbits) at17f080a (8 mbits) pagesel = 00, page_en = 1 00000 ? 0ffffh 00000 ? 1ffffh pagesel = 01, page_en = 1 10000 ? 1ffffh 20000 ? 3ffffh pagesel = 10, page_en = 1 20000 ? 2ffffh 40000 ? 5ffffh pagesel = 11, page_en = 1 30000 ? 3ffffh 60000 ? 7ffffh pagesel = xx, page_en = 0 00000 ? 3ffffh 00000 ? 7ffffh
6 2823d?cnfg?2/08 at17f040a/080a 5.10 ready open collector reset state indicator. driven low during power-up reset, released when power-up is complete. (recommended 4.7 k ? pull-up on this pin if used). 5.11 ser_en (1) the serial enable input must remain high during fpga configuration operations. bringing ser_en low enables the 2-wire serial programming mode. for non-isp applications, ser_en should be tied to v cc . 5.12 v cc +3.3v (10%). notes: 1. this pin has an internal 20 k ? pull-up resistor.
7 2823d?cnfg?2/08 at17f040a/080a 6. fpga master serial mode summary the i/o and logic functions of any sram-based fpga are established by a configuration pro- gram. the program is loaded either automatical ly upon power-up, or on command, depending on the state of the fpga mode pins. in master mode, the fpga automatically loads the config- uration program from an external memory. th e at17fxxxa serial configuration prom has been designed for compatibility wi th the master serial mode. this document discusses the atmel at40k, at 40kal and at94kal applications as well as altera applications. 7. control of configuration most connections between the fpga device and t he at17fxxxa serial configurator prom are simple and self-explanatory. the data output of the at17fxxxa series conf igurator drives din of the fpga devices. the dclk output of the at17fxxxa device drives the dclk input data of the fpga. the ncasc output of a at17fxxxa series conf igurator drives the ncs input of the next configurator in a cascade chain of configurator devices. ser_en must be at logic high level (internal pull-up resistor provided) except during isp. the ready pin is available as an open-collector i ndicator of the device?s reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. page_en must remain low if download paging is not desired. if paging is desired, page_en must be high and the pagesel pins must be set to high or low such that the desired page is selected, see table 5-2 on page 5 . 8. cascading serial configuration devices for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configuration memories, cascaded configurators provide additional memory. after the last bit from the first configurator is r ead, the clock signal to the configurator asserts its ncasc output low and disables its data line dr iver. the second configurator recognizes the low level on its ncs input and enables its data output. after configuration is complete, the address coun ters of all cascaded configurators are reset if the reset /oe on each configurator is dr iven to its active (low) level. if the address counters are not to be reset upon completion, then the reset /oe input can be tied to its inactive (high) level. 9. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be pro- grammed by the 2-wire serial bus. the programming is done at v cc supply only. programming super voltages are generated in side the chip. the at17fxxxa parts are read/write at 3.3v nom- inal. refer to the at17fxxxa programming spec ification available on the atmel web site (www.atmel.com) for more programming detai ls. at17fxxxa devices are supported by the atmel atdh2200 programming system along with many third party programmers.
8 2823d?cnfg?2/08 at17f040a/080a 10. standby mode the at17fxxxa series configurators enter a low-power standby mode whenever ser_en is high and ncs is asserted high. in this mode, t he at17fxxxa configurator typically consumes less than 1 ma of current at 3.3v. the output remains in a high-impedance state regardless of the state of the oe input. 11. absolute maximum ratings* operating temperature..... .............................. -40 c to +85 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not im plied. exposure to abso- lute maximum rating co nditions for extended periods of time may affect device reliability. storage temperature .... ..................... ........... -65 c to +150 c voltage on any pin with respect to ground ....... .......................-0.5v to v cc +0.5v supply voltage (v cc ) ...................... ...................-0.5v to +4.0v maximum soldering temp. (10 sec. @ 1/16 in.)............ 260 c esd (r zap = 1.5k, c zap = 100 pf)............ ..................... 2000v 12. operating conditions symbol description at17fxxxa series configurator units min max v cc commercial supply voltage relative to gnd -0 c to +70 c 2.97 3.63 v industrial supply voltage relative to gnd -40 c to +85 c 2.97 3.63 v 13. dc characteristics symbol description at17f040a at17f080a units min max min max v ih high-level input voltage 2.0 v cc 2.0 v cc v v il low-level input voltage 0 0.8 0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) commercial 2.4 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 0.4 v v oh high-level output voltage (i oh = -2 ma) industrial 2.4 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 0.4 v i cca supply current, active mode at freq. max. 50 50 ma i l input or output leakage current (v in = v cc or gnd) -10 10 -10 10 a i ccs supply current, standby mode commercial 3 3 ma industrial 3 3 ma
9 2823d?cnfg?2/08 at17f040a/080a 14. ac characteristics 15. ac characteristics when cascading ncs reset/oe clk data t sce t lc t hc t cac t oe t ce t oh t hoe t sce t hce t df t oh ncs reset/oe clk data ncasc t cdf t ock t oce t oce t ooe last bit first bit
10 2823d?cnfg?2/08 at17f040a/080a notes: 1. preliminary specifications for military operating range only. 2. ac test lead = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. 4. see the at17fxxxa programming spec fication for procedural information. 16. ac characteristics symbol description at17f040a/080a units min typ max t oe (2) oe to data delay commercial 50 ns industrial (1) 55 ns t ce (2) ncs to data delay commercial 55 ns industrial (1) 60 ns t cac (2) dclk to data delay commercial 30 ns industrial (1) 30 ns t oh data hold from ncs, oe, or dclk commercial 0 ns industrial (1) 0ns t df (3) ncs or oe to data float delay commercial 15 ns industrial (1) 15 ns t lc dclk low time commercial 15 ns industrial (1) 15 ns t hc dclk high time commercial 15 ns industrial (1) 15 ns t sce ncs setup time to dclk (to guarantee proper counting) commercial 20 ns industrial (1) 25 ns t hce ncs hold time from dclk (to guarantee proper counting) commercial 0 ns industrial (1) 0ns t hoe reset /oe low time (guarantees counter is reset) commercial 20 ns industrial (1) 20 ns f max maximum input clock frequency seren = 0 commercial 10 mhz industrial (1) 10 mhz t wr write cycle time (4) commercial 12 s industrial (1) 12 s t ec erase cycle time (4) commercial 13 s industrial (1) 13 s
11 2823d?cnfg?2/08 at17f040a/080a notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. note: 1. airflow = 0 ft/min. 16.1 ac characteristics when cascading symbol description at17f040a at17f080a units min max min max t cdf (3) dclk to data float delay commercial 50 50 ns industrial 50 50 ns t ock (2) dclk to ncasc delay commercial 50 50 ns industrial 55 55 ns t oce (2) ncs to ncasc delay commercial 35 35 ns industrial 40 40 ns t ooe (2) reset /oe to ncasc delay commercial 35 35 ns industrial 25 35 ns 17. thermal resistance coefficients package type at17f040a at17f080a 20j plastic leaded chip carrier (plcc) jc [ c/w] ? ja [ c/w] (1) ? 32a thin plastic quad flat package (tqfp) jc [ c/w] 17 17 ja [ c/w] (1) 62 62
12 2823d?cnfg?2/08 at17f040a/080a notes: 1. for the -30jc and -30ji package, cu stomers may migrate to the at17fxxxa-30ju. 18. ordering information memory size ordering code package (1) operation range 4-mbit at17f040a-30qc 32a - 32 tqfp commercial (0 c to 70 c) at17f040a-30qi 32a - 32 tqfp industrial (-40 c to 85 c) 8-mbit at17f080a-30qc 32a - 32 tqfp commercial (0 c to 70 c) at17f080a-30qi 32a - 32 tqfp industrial (-40 c to 85 c) 19. green package options (pb/halide-free/rohs compliant) memory size ordering code package operation range 4-mbit AT17F040A-30CU at17f040a-30ju 8cn4 -8 lap 20j - 20 plcc industrial (-40 c to 85 c 8-mbit at17f080a-30cu at17f080a-30ju 8cn4 -8 lap 20j - 20 plcc package type 8cn4 8-lead, 6 mm x 6 mm x 1.04 mm, lead less array package (lap) ? pin-compatib le with 8-lead soic/voic packages 20j 20-lead, plastic j-leaded chip carrier (plcc) 32a 32-lead, thin (1.0 mm) plastic quad flat package carrier (tqfp)
13 2823d?cnfg?2/08 at17f040a/080a 20. packaging information 20.1 8cn4 ? lap title drawing no. gpc rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 8cn4 dmh d 8cn4 , 8-lead (6 x 6 x 1.04 mm body), lead pitch 1.27mm, leadless array package (lap) 2/15/08 common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.45 0.50 0.55 1 d 5.89 5.99 6.09 e 5.89 5.99 6.09 e 1.27 bsc e1 1.10 ref l 0.95 1.00 1.05 1 l1 1.25 1.30 1.35 1 note: 1. metal pad dimensions. 2. all exposed metal area shall have the following finished platings. ni: 0.0005 to 0.015 mm au: 0.0005 to 0.001 mm pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
14 2823d?cnfg?2/08 at17f040a/080a 20.2 20j ? plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 9.779 ? 10.033 d1 8.890 ? 9.042 note 2 e 9.779 ? 10.033 e1 8.890 ? 9.042 note 2 d2/e2 7.366 ? 8.382 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01
15 2823d?cnfg?2/08 at17f040a/080a 20.3 32a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0. 8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pi n 1 ide n tifier 0?~7? pi n 1 l c a1 a2 a d1 d e e1 e b n otes: 1. this package conforms to jedec reference ms-026, v ariation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 8 .75 9.00 9.25 d1 6.90 7.00 7.10 n ote 2 e 8 .75 9.00 9.25 e1 6.90 7.00 7.10 n ote 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e0. 8 0 typ common dimensions (unit of measure = mm) symbol min nom max note
2823d?cnfg?2/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support configurator@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no lice nse, express or imp lied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site , atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its product s including, but not limited to, the implied wa rranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indire ct, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of pr ofits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of th e possibility of such damages. atmel makes no representations or warranties with re spect to the accuracy or comple teness of the contents of this document and reserves the rig ht to make change s to specifications and product descriptions at any time withou t notice. atmel does not make any commitmen t to update the information contained her ein. unless specifically provided otherwise, atmel products are no t suitable for, and shall not be used in, automotive applicatio ns. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other te rms and product names may be trademarks of others.

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